Also, we refer to the data inputs (S, R, and D, respectively) of these flip-flops as synchronous inputs, because they have effect only at the time of the clock pulse edge (transition), thereby synchronizing any output changes with that clock pulse, rather than at the whim of the data inputs.īut, how do we actually accomplish this edge-triggering? To create a “gated” S-R latch from a regular S-R latch is easy enough with a couple of AND gates, but how do we implement logic that only pays attention to the rising or falling edge of a changing digital signal? The enable signal is renamed to be the clock signal. Consequently, and edge-triggered S-R circuit is more properly known as an S-R flip-flop, and an edge-triggered D circuit as a D flip-flop. Whenever we enable a multivibrator circuit on the transitional edge of a square-wave enable signal, we call it a flip-flop instead of a latch. There is such a thing as negative edge triggering as well, and it produces the following response to the same input signals: This is known as positive edge-triggering. In the second timing diagram, we note a distinctly different response in the circuit output(s): it only responds to the D input during that brief moment of time when the enable signal changes, or transitions, from low to high. When the enable signal falls back to a low state, the circuit remains latched. In the first timing diagram, the outputs respond to input D whenever the enable (E) input is high, for however long it remains high. Let’s compare timing diagrams for a normal D latch versus one that is edge-triggered: D Latch Timing Diagram One method of enabling a multivibrator circuit is called edge triggering, where the circuit’s data inputs have control only during the time that the enable input is transitioning from one state to another. In many digital applications, however, it is desirable to limit the responsiveness of a latch circuit to a very short period of time instead of the entire duration that the enabling input is activated. The latch responds to the data inputs (S-R or D) only when the enable input is activated. So far, we’ve studied both S-R and D latch circuits with enable inputs.
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